1. Field of the Invention
The present invention relates to a semiconductor device having a structure in which a plurality of semiconductor devices are stacked.
2. Description of the Related Art
In recent years, demand for larger memory capacity has further increased. However, due to factors, such as the larger scale, the complexity of peripheral circuits, and the difficulty of shortening of manufacturing process, it is difficult to decrease the area of a semiconductor chip. To achieve larger capacity and higher integration, Japanese Patent Laid-Open No. 2007-165454 describes a chip-stacked-type semiconductor device in which the same or different types of semiconductor chips are stacked.
Also, a stacked-type semiconductor device in which a plurality of semiconductor devices are stacked is known (see Japanese Patent Laid-Open No. 2005-26680). In the stacked-type semiconductor device described in Japanese Patent Laid-Open No. 2005-26680, a plurality of semiconductor devices having a BGA (Ball Grid Array) structure are stacked. Further, a semiconductor device having an sFBGA (stacked FBGA) structure that is a stacked-type semiconductor device in which a plurality of semiconductor devices of an FBGA (Fine pitch Ball Grid Array) structure are stacked is also known.
For high-speed DRAM (Dynamic Random Access Memory), such as DDR2 (Double Data Rate 2) and DDR3 (Double Data Rate 3), a standard for the arrangement of the external connection terminals (for example, solder balls) of a semiconductor device is provided by JEDEC (Joint Electron Device Engineering Council) that is an industry organization promoting the standardization of electronic parts. The restriction on the positions of the connection terminals according to this standard is one of the factors that account for the difficulty in improving the mechanical reliability of the semiconductor device.
Restrictions, such as the JEDEC standard, apply to the positions of external connection terminals which are used to connect the above described stacked-type semiconductor device to a motherboard. Also, inter-board connection terminals (for example, solder balls) that connect the wiring boards of adjacent semiconductor devices among stacked semiconductor devices are arranged to avoid a lower-layer semiconductor chip. Therefore, generally, the arrangement of the above external connection terminals and the arrangement of the above inter-board connection terminals are different.
In the stacked-type semiconductor device, due to a difference in the linear expansion coefficient between the semiconductor chip and the wiring board, warpage is caused by heat during use. Such warpage applies a load to the connection terminals and therefore is one factor that accounts for a reduction in the connection life of the connection terminals.
Japanese Patent Laid-Open No. 2007-165454 describes a configuration in which warpage is reduced in a chip-stacked-type semiconductor device in which a plurality of semiconductor chips having different sizes are stacked on a wiring board. This chip-stacked-type semiconductor device comprises a dummy chip on the top-layer semiconductor chip. The dummy chip and the plurality of semiconductor chips are sealed together by resin. The amount of resin on the semiconductor chips is reduced by the dummy chip, so that warpage is relieved.
However, in the chip-stacked-type semiconductor device described in Japanese Patent Laid-Open No. 2007-165454, the plurality of semiconductor chips are sealed together by resin, so that if even one malfunctioning semiconductor chip is present, all semiconductor chips become unusable.
Japanese Patent Laid-Open No. 2005-26680 describes a stacked-type semiconductor device in which a plurality of semiconductor devices are stacked. In the stacked-type semiconductor device described in Japanese Patent Laid-Open No. 2005-26680, due to a difference in linear expansion coefficient between the semiconductor chip and other members, the shear deformation of the connection terminals increases, so that reliability of the connection terminals decreases. In the stacked-type semiconductor device having an sFBGA structure, the plurality of semiconductor chips are not sealed together by resin. Thus, even if there is one malfunctioning semiconductor chip present, all of the other semiconductor chips will not become unusable.
Also, in the stacked-type semiconductor device having an sFBGA structure, the bottom-layer semiconductor device is bound to a motherboard by external connection terminals. Thus, the shear deformation of the connection terminals connecting the motherboard and the bottom-layer semiconductor device is reduced. However, semiconductor devices stacked above the bottom-layer semiconductor device are not bound to the motherboard. Therefore, a large difference in warpage between the bottom-layer semiconductor device and the semiconductor devices above the bottom-layer semiconductor device occurs. Therefore, a large load is applied to inter-board connection terminals that connect the semiconductor devices in layers. Due to this load, the connection life of the connection terminals decreases, and the reliability of the semiconductor device is reduced. Therefore, one problem is to ensure the reliability of the inter-board connection terminals that connect the semiconductor devices in layers to each other.
In the case of the stacked-type semiconductor device in which the positions of the external connection terminals and the positions of the inter-board connection terminals are different, as described above, the warpage of the semiconductor devices in layers is necessarily different. Therefore, there is a problem in which a large load is applied to the inter-board connection terminals, resulting in a reduction of the connection life.
In order to ensure the reliability of the inter-board connection terminals, it is effective to reduce the difference in warpage in adjacent semiconductor devices that are interconnected by the inter-board connection terminals.